Conventionally, voltage conversion devices for converting a voltage by driving a switching element using a PWM signal are widely used. For example, a voltage conversion device using this PWM control method calculates a voltage command value based on a target voltage value, and sets a value that corresponds to the calculated voltage command value for a PWM signal generating portion, thereby generating a PWM signal having a duty ratio that corresponds to the set value. By thus changing the duty ratio of the PWM signal for driving the switching element in accordance with the target voltage value, an output voltage that corresponds to the target voltage value is obtained.
In the case where switching elements that are driven by the PWM signal are bridge-connected, or in the case of synchronously rectifying a current that returns to a circuit having inductance in association with switching, a so-called dead time is provided from when one switching element turns off until the other switching element turns on so that two switching elements that are connected in series do not simultaneously turn on at any time.
Here, if a minimum increment (i.e. minimum unit) of a value that can be set for a PWM signal generating portion (hereinafter, “settable value”) is relatively large, the duty ratio of the PWM signal cannot be smoothly varied with respect to a change in the target value, and the output voltage will vary step-wise. For example, in the case where a target value that is to be set for the PWM signal generating portion is calculated as an amount of operation to be made under PWM control, when the minimum increment of the settable value is greater than the minimum increment of the target value, the duty ratio of the PWM signal cannot be smoothly varied with respect to a change in the target value and a load change, and an error occurs in the output voltage.
In this regard, JP H3-98470A discloses a PWM inverter in which, when the on/off-time of a PWM signal is computed in every PWM control period, the on/off-time is calculated by performing computation while rounding down the remainder of division using a voltage command value as a dividend, and a PWM pulse is output based on the calculation result. The remainder that occurs in the above computation corresponds to a voltage command value that is not reflected in the on/off-time and rounded down.
In this PWM inverter, the remainder that has been rounded down is sequentially added to the voltage command value in the computation in the next and subsequent periods. Thus, the remainder that was not reflected in the on/off-time in the previous computation is reflected in the new on/off-time at the time of the next computation, the remainder at this time is further reflected in the next computation, and this computation is repeated. As a result, the average value of the on/off-time that is to be set for the PWM generating portion can be brought close to a target on/off-time that is to be originally set. That is to say, the minimum increment of the value set for the generating portion can be set smaller than the actual increment in average.
However, with the technique disclosed in JP H3-98470A, computation that includes division is executed in every PWM control period to determine the on/off-time of the PWM signal, and accordingly, a significant processing load occurs in every period. In addition, in JP H3-98470A, consideration is not given to the aforementioned dead time. For this reason, to secure a certain dead time, the on-time of PWM signals for at least two switching elements included in an inverter needs to be separately calculated. Therefore, with a cheap microcomputer with poor processing capability, there is a concern that the aforementioned computation processing and other processing, such as communication, cannot be stably executed in parallel, even if a change in the target value is relatively small.
The present invention has been made in view of the foregoing situation, and aims to provide a signal generation circuit in which a minimum increment of a value to be set for a generating portion, which periodically generates a first signal having an on-time corresponding to a set value, and a second signal having an on-period that does not overlap the on-period of the first signal, can be made substantially smaller than an actual increment with a relatively small processing load, as well as a voltage conversion device and a computer program.